This invention relates to digital to analog converters (ADCs), and more particularly to a distributed resistor ladder structure for use with flash ADCs.
ADCs are typically utilized to sample an analog electronic signal at a point in time and convert it to a digitized representation thereof. The ADC, in one common configuration, typically includes a resistive ladder network electrically coupled to a plurality of comparators that are each referenced to one of a plurality of reference voltages provided by the resistive network. The ADC compares the voltage amplitude of the analog input signal to the plurality of reference voltages to determine the reference voltage closest in value to that of the input signal.
In greater detail, and with reference to FIG. 1, the fundamental block level architecture of a typical flash ADC 1 includes a resistor ladder of resistors 10, each of which provides a reference voltage to one of a plurality of comparators 12 coupled to an encoder and error correction circuit 14. The resistor ladder is supplied with voltages Vref+ and Vref− to create the quantization reference voltages. Each comparator compares the input signal 20 to its respective reference voltage and provides a signal d1 . . . N to the encoder 14 indicative of the voltage of the input signal. The encoder then calculates the value of the input signal voltage based upon the signals d1 . . . N received from all the comparators and outputs a digital signal D indicative of this value.
The first and last resistors 10 in the ladder typically have a resistance of R/2, which produces a first reference voltage at half the quantization stage. The other resistors have a resistance value of R, corresponding to a voltage representing one full quantization stage. The total number of resistors is therefore 2n+1, where n is the resolution of the ADC. Assuming a potential difference over the entire ladder of V, a total current of Itot will be flowing through the resistors, according to equation 2.
                    V        =                  (                                    V                              ref                +                                      -                          V                              ref                -                                              )                                    (                  Eq          .                                          ⁢          1                )                                          I          tot                =                  V                      (                          R              ×                              2                n                                      )                                              (                  Eq.  2                )            
Due to a leakage current Ib at the input of each comparator 12, a bowing effect appears along the ladder that causes distortion in the integrity and equality of the quantization levels. As a result, the current through a resistor “m” is defined by equation 3.
                              I          m                =                              V                          (                              R                ×                                  2                  n                                            )                                -                      m            ×                          I              b                                                          (                  Eq          .                                          ⁢          3                )            
To decrease the relative degree of the bowing, the resistivity of each resistor must be determined for the current drop-out and/or the input leakage current Ib must be scaled. In addition, Itot/Ib must be high enough to allow an acceptable drop in the reference voltage when the comparator switches and the current gain of the input transistor drops. The degree of degradation increases as the sampling frequency is raised.
As the breakdown voltage in high-speed technologies keeps decreasing, the supply voltage is dropping as well. As a result, to increase the total current available, resistance values must be decreased. Thus, the physical size and the parasitics of the resistors are becoming significant variables in the determination of resistor value and tend to quickly become destructive, thereby causing a loss of resolution. Additionally, in current ADCs the interconnects carrying the reference voltages by necessity must cross the interconnect carrying the analog input signal, which causes further signal dependent distortion of the input to the comparator cells that degrades the dynamic characteristics of the converter. This effect is especially apparent in wide-band ADCs.
As evident from the above discussion, the resistors in the resistor ladder of an ADC should have very precise resistance values for the ADC to function properly and accurately. Resistance variations as low as 0.025 percent can compromise the linearity and accuracy of a 12-bit ADC. However, the standard semiconductor circuit manufacturing techniques used to manufacture ADCs often produce resistors with resistance mismatches of as much as 0.2 percent, necessitating further post-production processing. One technique well known in the art entails trimming the resistors with lasers to a precise resistance. This is currently not a financially viable method for producing high volume, medium-cost ADCs. Another approach known in the art to correct for ADC non-linearities is to store a table of correction values in a memory and use computer software to adjust each digital value output by the ADC with a corresponding correction value read from the stored table. This technique is not practicable when a microprocessor or microcontroller is not used in the particular application or system, or when the system lacks sufficient memory storage or microprocessor computation cycles to use this technique.
What is now needed is an improved, cost effective method for generating precise reference voltages for the comparators of an ADC. The embodiments disclosed herein address this and other needs.